Analog to digital converter
In electronics, an analog to digital converter (abbreviated ADC, A/D, or A to D) is a device that converts continuous signals to discrete digital numbers. Typically, an ADC converts a voltage to a digital number. The digital to analog converter or DAC performs the reverse operation.
The resolution of the converter indicates the number of discrete values it can produce. It is usually expressed in bits. For example, an ADC that encodes an analog input to one of 256 discrete values has a resolution of eight bits, since
- 28 = 256.
Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of quantization levels. Some examples may help:
- Example 1
- Full scale measurement range = 0 to 10 volts
- ADC resolution is 12 bits: 212 = 4096 quantization levels
- ADC voltage resolution is: (10-0)/4096 = 0.00244 volts = 2.44 mV
- Example 2
- Full scale measurement range = -10 to +10 volts
- ADC resolution is 14-bits: 214 = 16384 quantization levels
- ADC voltage resolution is: (10-(-10))/16384 = 20/16384 = 0.00122 volts = 1.22 mV
Most ADCs are linear, which means that they are designed to produce an output value that is a linear function of, i.e. proportional to, the input. Another common type is the logarithmic ADC, which is used in voiced communication system s to increase the entropy of the digitalized signal.
The histogram of a speech signal has the shape of two decreasing exponentials, and the non-linear ADCs try to aproximate this to a square PDF using functions as the a-law or the μ-law which are logarithmic functions. The distorted signal has a lower dynamic range, and its quantization adds less noise to the original signal then a linear quantization with the same input range and resolution.
Accuracy depends on the error in the conversion. If the ADC is not broken, this error has two components: quantization error and (assuming the ADC is intended to be linear) non-linearity. These errors are measured in a unit called the LSB, which is an abbreviation for least significant bit. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.
Quantization error is due to the finite resolution of the ADC, and is an unavoidable imperfection in all types of ADC. The magnitude of the quantization error at the sampling instant is between zero and half of one LSB.
All ADCs suffer from non-linearity errors caused by their physical imperfections, causing their output to deviate from a linear function (or some other function, in the case of a deliberately non-linear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing.
Important parameters for linearity are integral non-linearity (INL) and differential non-linearity (DNL).
The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate of the converter.
The key idea here is that a continuously varying bandlimited signal can be sampled (i.e. the signal values at intervals of time T, the sampling time, are measured and stored) and then the original signal can be EXACTLY reproduced from the discrete-time values by an interpolation formula. The accuracy is however limited by quantization error. However this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency component present in the signal. This is essentially what is embodied in the Shannon-Nyquist sampling theorem.
Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task - in most cases by using a capacitor to store the analogue voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.
All ADCs work by sampling their input at discrete intervals of time. Their output is therefore an incomplete picture of the behaviour of the input. There is no way of knowing, by looking at the output, what the input was doing between one sampling instant and the next. If the input is known to be changing slowly compared to the sampling rate, then it can be assumed that the value of the signal between two sample instants was somewhere between the two sampled values. If, however, the input signal is changing fast compared to the sample rate, then this assumption is not valid.
If the digital values produced by the ADC are, at some later stage in the system, converted back to analog values by a digital to analog converter or DAC, it is desirable that the output of the DAC is a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is the difference between the signal frequency and the sampling rate. For example, a 2 kHz sinewave being sampled at 1.5 kHz would be reconstructed as a 500 Hz sinewave. This problem is called aliasing.
To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system.
There are four common ways of implementing an electronic ADC:
- A direct conversion ADC or flash ADC has a comparator that fires for each decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has only 8 bits of resolution (256 comparators) or less. ADCs of this type have a large die size, a high input capacitance, and are prone to produce glitches on the output (by outputting an out-of-sequence code). They are often used for video or other fast signals.
- A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. For example, the first comparison might decide the most significant bit of the output, the next comparison decides the next-most significant bit, etc. This is also called bit-weighting conversion. ADCs of this type convert very fast, and have good resolutions and quite wide ranges. They are more complex than some other designs.
- A delta-encoded ADC has an up-down counter that feeds a digital to analog converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but the conversion time is dependent on the input signal level, though it will always have a guaranteed worst-case. Delta converters are often very good choices to read real-world signals. Most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are known to be small in magnitude.
- A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value.
- A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This type of ADC is fast, has a high resolution and only requires a small die size.
Nonelectronic ADCs usually use some scheme similar to one of the above.
Commercial Analog to Digital converters
These are usually integrated circuits.
Most converters sample with 6 to 24 bits of resolution, and produce fewer than 1 megasample per second. Mega- and gigasample converters are available, though (Feb 2002); megasample converters are required for digital video editing . Commercial converters usually have ±0.5 to ±1.5 LSB error in their output.
The most expensive part of an integrated circuit is the pins, because that makes the package larger, and each pin has to be connected to the integrated circuit's silicon. To save pins, it's common for ADCs to send their data one bit at a time over a serial interface to the computer, with the next bit coming out when a clock signal changes state, say from zero to 5V. This saves quite a few pins on the ADC package, and in many cases, does not make the overall design any more complex. (A notable exception is in connecting the converters to microprocessors which use memory-mapped IO.)
Commercial ADCs often have several inputs that feed the same converter, usually through an analog multiplexer. Different models of ADC may include sample-and-hold circuits, instrumentation amplifiers or differential inputs, where the quantity measured is the difference between two voltages.